The present invention relates to semiconductor integrated circuit devices that include a plurality of internal memories and a plurality of processing units for data processing, and that operate while being connected to an external processing unit.
JP H10-27131A discloses a shared memory device performing conflict control for DMA transfer requests from a plurality of communication controllers, wherein even while one memory bank is being used, access to other memory banks is possible, and thus the frequency that the communications controllers are caused to wait by shared memory access is reduced.
JP H10-260952A discloses a technology for flexibly connecting the processors and the memory banks in a multiprocessor system LSI with an integrated multibank memory.
JP 2000-99391A discloses a printer device, in which memory banks can be accessed simultaneously by mediating access to the memory banks of a memory individually for each memory bank.
JP 2001-43180A discloses a microprocessor in which a plurality of resources share a single memory, and no-wait access is possible in parallel.
There is thus a need for memory allocation to various processing units in semiconductor integrated circuit devices that include a plurality of internal memories and a plurality of processing units for data processing, and that operate while being connected to an external processing unit.